1. Field of the Invention
The present invention pertains to a device for the self-synchronization of the output circuits of a memory. It pertains more especially to a device for the self-synchronization of the output circuits of a memory comprising a so-called "3-state" gate enabling a high-impedance state.
2. Description of the Prior Art
Most memories used today, i.e. both ROMs (read-only memories) and RAMs (random-access memories), use output circuits that have a high impedance state, i.e. they are capable of adopting an indeterminate level corresponding to an output disconnected from the circuit. This high impedance state enables the parallel connection of the outputs of several circuits, only one of which is put into operation at a time. Generally, this high impedance state is monitored by using a combinational logic circuit, the propagation characteristics of which are unrelated to the characteristics of the output logic. This combinational logic circuit generally comprises logic gates controlled by signals such as the output control signals E, W, EO. As a result of using this type of circuit, the change from high impedance to low impedance occurs very early in the read and write cycle. This leads to a number of unwanted commutations in the output stages. For, at that moment, the read amplifiers are incapable of giving useful information.
These unwanted commutations have the following disadvantages:
Unnecessary congestion of the output bus which may penalize the system in which the memory is integrated,
Current surges internal to the circuit, resulting from the commutations of the output stages formed by power transistors having a width of several hundreds of microns. These current surges generate a particularly troublesome noise for the circuit which is then in a stage of amplification of small signals. Consequently, the efficiency of the system may be greatly reduced.